1. Field of the Invention
The present invention relates to a method of manufacturing an SOI (silicon-on-insulator) wafer used as a substrate for a semiconductor device.
2. Description of the Background Art
Among methods of manufacturing SOI wafers is a bonding method. In this method, two silicon wafers, at least one of which has a silicon oxide film formed thereon, are bonded to each other with the silicon oxide film interposed therebetween, and thereafter, one of the silicon wafers is made into a thin film, thereby forming a silicon layer (hereinafter referred to as “element forming layer”) on which a semiconductor element is to be formed. Among thin-film techniques for silicon wafers, methods are known such as chemical-mechanical polishing, bonding and etch back, and hydrogen implanting separation (Smart-Cut: registered trademark).
In the chemical-mechanical polishing, a silicon wafer to be an element forming layer is made into a thin film by polishing using an abrasive cloth and an alkaline solution including abrasive particles (particles of the silicon oxide, etc). In the bonding and etch back, a layer (an impurity layer of high concentration, a porous silicon layer, and the like) having an etching rate different from that of a silicon wafer to be an element forming layer is formed beforehand on the silicon wafer, and the silicon wafer is made into a thin film by chemical etching using hydrofluoric acid or a liquid mixture of hydrofluoric acid and nitric acid. In the hydrogen implanting separation, hydrogen is implanted beforehand into a silicon wafer to be an element forming layer to form a hydrogen implanted layer, and the hydrogen implanted layer is separated by heat treatment at about 500° C., thereby making the silicon wafer into a thin film.
FIGS. 31 through 39 show a conventional method of manufacturing an SOI wafer in sequential order. Referring to FIG. 31, prepared first is a silicon wafer 101 to be a supporting substrate of the SOI wafer. The silicon wafer 101 has a first main surface 101a and a second main surface 101b. Referring to FIG. 32, prepared further is a silicon wafer 102 to be an element forming layer of the SOI wafer. The silicon wafer 102 has a first main surface 102a and a second main surface 102b. An insulation layer 103 made of a silicon oxide film is formed on the first main surface 102a of the silicon wafer 102. The insulation layer 103 may be formed on the entire surface of the silicon wafer 102. Next, referring to FIG. 33, the silicon wafers 101 and 102 are bonded to each other with the insulation layer 103 interposed therebetween, thereby forming a wafer 150 in which the silicon wafer 101, the insulation layer 103 and the silicon wafer 102 are laminated in this order (the wafer 150 is hereinafter referred to as “laminated wafer”).
Next, to improve the bonding strength between the silicon wafers 101 and 102, heat treatment (anneal at about 1000° C.) is conducted. More specifically, using a horizontal diffusion furnace shown in FIG. 34, a boat 151 with a plurality of laminated wafers 150 mounted thereon is transferred into a quartz tube 152, where the laminated wafers 150 are heated by a heater 153. Alternatively, using a vertical diffusion furnace shown in FIG. 35, a boat 154 with the plurality of laminated wafers 150 mounted thereon is transferred into a quartz tube 155, where the laminated wafers 150 are heated by a heater 156.
FIGS. 36 and 37 show the inside of the horizontal diffusion furnace shown in FIG. 34. A plurality of wafer supporting parts 158 are formed on a bottom 157 of the boat 151, and the laminated wafers 150 are supported by the wafer supporting parts 158. The wafer supporting parts 158 are band-like members 159 with a plurality of recesses 160 formed thereon at regular intervals. As shown in FIG. 37, the second main surface 101b of the silicon wafer 101 is in contact with a side surface 160s1 of one of the recesses 160, and a side surface of the silicon wafer 101 is in contact with a bottom surface 160b of one of the recesses 160. The second main surface 102b of the silicon wafer 102 is in contact with a side surface 160s2 of one of the recesses 160, and a side surface of the silicon wafer 102 is in contact with the bottom surface 160b of one of the recesses 160.
FIGS. 38 and 39 show the inside of the vertical diffusion furnace shown in FIG. 35. FIG. 39 shows a sectional structure taken along the line X100—X100 shown in FIG. 38. The laminated wafers 150 are supported by a plurality of wafer supporting parts 161 included in the boat 154. The wafer supporting parts 161 are band-like members 162 with a plurality of recesses 163 formed thereon at regular intervals. As shown in FIG. 39, the second main surface 101b of the silicon wafer 101 is in contact with a bottom surface 163b of one of the recesses 163, and the side surface of the silicon wafer 101 is in contact with a side surface 163s of one of the recesses 163. The side surface of the silicon wafer 102 is in contact with the side surface 163s of one of the recesses 163.
After conducting heat treatment for improving the bonding strength, the silicon wafer 102 is made into a thin film from the side of the second main surface 102b using the above-described chemical-mechanical polishing or the like. Accordingly, an element forming layer is formed and an SOI wafer is completed.
However, the aforementioned conventional method of manufacturing an SOI wafer has the following problem. FIGS. 40 and 41 are explanatory views of the problem in the conventional method of manufacturing an SOI wafer. As shown in FIG. 37, the side surface of the silicon wafer 101 to be a supporting substrate of the SOI wafer and that of the silicon wafer 102 to be an element forming layer of the SOI wafer are both in contact with the bottom surface 160b of one of the recesses 160. Further, as shown in FIG. 39, the side surface of the silicon wafer 101 and that of the silicon wafer 102 are both in contact with the side surface 163s of one of the recesses 163. Therefore, each side surface of the silicon wafers 101 and 102 receives a scratch due to the contact with the recesses 160 and 163, so that scratch receiving parts 125a and 125b are formed, as shown in FIG. 40.
The scratch receiving part 125a formed on the silicon wafer 102 is removed in the process of making the silicon wafer 102 into a thin film, as shown in FIG. 41. However, the scratch receiving part 125b formed on the silicon wafer 101 is not removed in that process and thus remains on an SOI wafer 127 finally manufactured. The scratch receiving part 125b causes a reduction of toughness of the SOI wafer 127, resulting in a problem in that the scratch receiving part 125b causes a heat crack in the SOI wafer 127 during the process of forming a semiconductor element in an element forming layer 126 of the SOI wafer 127.
Moreover, the laminated wafers 150 are supported only by the wafer supporting parts 158 and 161 of the boats 151 and 154, which causes the self weight of the laminated wafers 150 to concentrate on contact parts with the wafer supporting parts 158 and 161, resulting in an occurrence of a slip dislocation. In particular, the laminated wafers 150 each including two silicon wafers 101 and 102 have such a great weight that the occurrence of the slip dislocation is promoted. The slip dislocation also causes a reduction of toughness of the SOI wafer 127 similarly to the above-described scratch receiving part 125b, which results in the problem as described above.